1. Field of the Invention
This invention relates to a non-volatile semiconductor storage system that is electrically rewritable.
2. Description of the Related Art
As an example of a storage medium that can store data in a non-volatile manner, a NAND type flash memory is known.
A cell array of a NAND flash memory is composed of NAND cell units each having a plurality of memory cells connected in series. Each of the NAND cell units has both ends each of which is connected to a bit line or a source line through a selection gate transistor.
Control gates of the memory cells in the NAND cell unit are connected to different word lines, respectively. In a NAND flash memory, a plurality of memory cells share source regions and drain regions, and are connected in series. Also, the plural memory cells share a selection gate transistor, a bit line contact and a source line contact. Accordingly, a size per a unit memory cell can be reduced.
Furthermore, since a word line and a device region of memory cells are formed to have a shape of a simple stripe, the NAND flash memory is easy to be miniaturized. Thus, a flash memory having a large capacity is realized. In recent years, such a NAND flash memory is used in so-called SSD (Solid-State-Drive), and is expected as a large-capacitance storage device that may substitute hard disk drives in personal computers or the like.
By the way, when data write or data erase is repeatedly conducted to a memory cell many times, charges trapped in a charge accumulation film of the memory cell gradually become hard to flow out. In that case, even if an erase operation is repeated the same number of times as before, a threshold voltage of the memory cell does not easily drop. On the other hand, in a write operation, the threshold voltage of the memory cell may easily be raised. Therefore, the difference in the number of data write/erase operation may cause variation in cell characteristic among the memory cells, thus decreasing the reliability thereof. This problem becomes more serious as the memory cell is further miniaturized.
In view of such a problem, the JP 2008-47273A discloses a control circuit for managing, per block or per page, a state of deterioration in characteristic of a memory cell that depends on the number of data erase/data write therefor.
However, for example, providing such a control circuit per memory chip will cause high cost of these memory chips and increase the chip area.